Duty Cycle Adjusting Circuit for Clock Signals
نویسنده
چکیده
A duty cycle control circuit for clock signals is presented. The proposed circuit uses a rising edge detector to generate one shot output signals which have the same frequency of the input clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses. By the feedback control voltage from an operational amplifier, the pulse width of generated rectangular pulses is automatically adjusted to a pre-set duty cycle. As compared to prior arts, features of this proposed circuit include simple design, low cost and less power. Key-Words: Duty cycle, Clock, Edge detector, Pulse width control, Monostable, One shot
منابع مشابه
Novel Frequency Doubler Circuits and Dividers Using Duty Cycle Control Buffers
Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors and two duty cycle control buffers a low cost frequency doubler circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input clock signal with an unpredictable duty cycle is inputted to a rising (or falling) edge detector. The edge detector converts the ...
متن کاملA 3.2Gb/s Clock and Data Recovery Circuit Without Reference Clock for a High-Speed Serial Data Link
A 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial link without the reference clock is described. The CDR has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate frequency detector that can achieve low-jitter operation and improve pull-in range. The PD of oversamping method finds a phase error by generati...
متن کاملA Clock Fault Detection Circuit for Nano-system by Time-to-Voltage Conversion
With the high complexity and density of future nano-system, many aspects such as synchronization system control and system test will be difficult to manage. Clock signals will be suffer from low power supplying and high structural broking rate. As a result, clock fault become an inevitable problem in nano-circuits Self-detection and selfrecovery for clock signal in systems are an important fiel...
متن کاملSerbian Journal of Electrical Engineering
The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system’s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a mul...
متن کاملHigh Performance Digital Pulsewidth-Control Circuit With Programmable Duty Cycle
In High speed operations the duty cycle of the clock signal is to bé calibrated at 50%. But the variations in process, voltage and temperature (PVT) influences the duty cycle and make it difficult to calibrate the duty cycle at 50%. To overcome this deviation Pulse width control loops (PWCLs) are used. This work presents a high performance and fast locking all digital pulse width control circui...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2005